1. Field of the Invention
The present invention relates generally to a semiconductor memory device having a surface strap, and a method of fabricating the semiconductor memory device, and more particularly to a DRAM (Dynamic Random Access Memory) having a trench capacitor. This invention is applied to a fin-gate trench-type DRAM.
2. Description of the Related Art
In recent years, with a decrease in cell size due to reduction in design rules, a channel width, which is an important parameter for determining a current drive power of a cell transistor, has decreased and a drive power has lowered. In order to suppress such lowering in driving power of the cell transistor, a trench-type DRAM cell using a fin-gate-type double-gate transistor is proposed (e.g. Jpn. Pat. Appln. KOKAI Publication No. 2002-118255).
In a prior-art fabrication process of forming the trench-type DRAM, there is a case where after a gate electrode of a cell transistor is processed, a spacer SiN film is formed on a side wall of the gate electrode to provide a source/drain region with an LDD (Lightly. Doped Drain) structure. At this time, in the case of a fin-gate cell transistor, the SiN film is also formed on a side wall of an activation region (source/drain region) at a position deeper than the major surface of the semiconductor substrate. As a result, when the trench capacitor and one of activation regions of the cell transistor are electrically connected by a surface strap, contact is made only at a substrate surface portion.
FIG. 1 is a cross-sectional view schematically showing the structure of a contact area between a trench capacitor and a source region of a cell transistor in a trench-type DRAM using the conventional fin-gate-type double-gate transistor.
FIG. 1 is an enlarged view showing a pillar FIN formed in a major surface portion of a semiconductor substrate 111, an STI oxide film 100 serving as a device isolation region, a source region 101 formed in the pillar FIN, a surface strap 102, an SiN film 103 formed at a side wall portion of the pillar FIN, a barrier SiN film 104, and a BPSG film 105.
In a contact side-wall portion 106 encircled by a broken line, a portion of the SiN film 103, which is formed as the spacer SiN film-on the side wall of the gate electrode, is left, and the surface strap 102 is electrically connected to the source region-101 only at an upper surface thereof (i.e. an upper surface of the pillar FIN). Thus, contact resistance between the surface strap 102 and source region 101 increases.
Recently, to meet a demand for miniaturization, the width of the pillar FIN and activation region is reduced. Consequently, with the prior-art structure wherein contact is made only at the surface of the pillar, the contact area between the surface strap and source region decreases and the contact resistance increases. This may lead to a deterioration in data storage characteristics and data write speed of the DRAM.